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5 bit current steering low power DAC for threshold voltage adjustment

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Phd student
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Physics & Astronomy
5 bit current steering low power DAC for threshold voltage adjustment
In this paper a low power integrated circuit of 5 bit current steering DAC is presented. The proposed DAC is integrated to prototype the readout channel for muon chamber in international CBM experiment at accelerated facility FAIR. DAC was implemented with an area of 0.019 mm2 using UMC MMRF 180 nm CMOS process. This DAC has ultralow power consumption - 25μW. The measured maximum differential nonlinearity (DNL) is 0.25 LSB (less significant bit), integral nonlinearity (INL) is 0.2 LSB. In this paper the main steps of design flow, simulation and measurement results are presented.
DAC, ASIC, readout channel

A prototype readout channel for CBM experiment was designed and manufactured by the UMC 180 nm CMOS technology. The structure of the channel is shown in figure 1 [7]. The analog part of channel includes a preamplifier, shaper, DAC, comparator and ADC. The comparator generates the start of conversion signal for ADC, when the signal from detector comes to the input of comparator. It is necessary to exclude false triggering by noise, so the threshold voltage of comparator must be adjustable. One of the most wide-spread methods of adjusting voltage is doing that by a digital to analog converter. Because of the large number of channels in one chip, the proposed DAC must be low power and efficient by area on chip. Also the threshold voltage adjustment must be quite accurate, so the proposed DAC must have a high linearity. Also the threshold voltage adjustment does not require a high speed of conversion. So the following requirements were formulated for the proposed DAC and presented in table 1.


Fig. 1. Prototype readout channel structure






Requirements for the proposed DAC


UMC 180 nm

Supply voltage

1.8 V


5 bits

Power consumption

<100 μW


<1 LSB


< 1 LSB


< 0.03 mm2



Design flow of the proposed DAC consists of five steps:

  1. Design of schematic.
  2. Simulation
  3. Design of layout
  4. Verification and parasitic elements extraction
  5. Simulation of verified schematic

The proposed DAC has a binary weighted architecture. This architecture was chosen because there is a special buffer before comparator, that produces a differential signal and adjust the threshold voltage proportionally to input current. Also there are only five current sources and a bias block, without any special buffers, so that the architecture is well suited for small resolution because of a low power consumption and small area on chip. Because of current sources, which are made on transistor level without resistors, that architecture provides a high linearity of output current.

The proposed DAC consists of a biasing circuit, current matrix and output stage. The DAC structure is presented in figure 2. The schematic of DAC was designed in the Cadence Virtuoso schematic editor. The biasing circuit produces bias voltages for the correct work of current matrix. Schematic of the bias is shown in figure 3. The main part of the DAC is a current matrix. It consists of five current sources.


Fig. 2. DAC structure


Fig. 3. Biasing circuit

One of the most important parameters of the current source is linearity. Transistor mismatch in current sources causes the nonlinearity of the DAC [1]. Increasing the area of transistors in current sources reduces nonlinearity [2], so the main transistors must have the maximum available channel length in the technology (50 μm). The series combination of current producing transistors M1 and M2 is implemented for the same unit current to achieve larger area and consequently a better matching and higher linearity. Another thing, which improves DAC nonlinearity, is a high output impedance of each current source. To increase output impedance a cascode transistor has been used. Because of the large area of main transistors M1 and M2, the output impedance is reduced.  Since the cascode transistor does not effect the output current, it will not contribute any mismatch. So the cascode transistor must have the minimum available channel length in the technology (180 nm). Also, to compensate the reduction of output impedance associated with the large current producing transistors, gain boosting has been used to increase the output impedance in each current cell [3]. To achieve enough output impedance the feedback path should be designed. The schematic of current source is presented in figure 4.



Fig. 4. Current source schematic


The main characteristics were simulated in Analog Design Environment (ADE) by using Monte-Carlo analysis. Since the designed DAC is static, the main static nonidealities, such as differential nonlinearity (DNL), integral nonlinearity (INL), gain error and offset, were simulated. DNL(k) is a vector that quantifies for each code k the deviation of this width from the "average" width (step size) [3]. DNL(k) is a measure of uniformity, it does not depend on gain and offset errors. Scaling and shifting a transfer characteristic does not alter its uniformity and hence DNL(k). DNL calculation [3], [4], [5]:



Integral nonlinearity is the maximum between transfer characteristic and a straight line drawn through the endpoints from each relevant point of transfer characteristic. Just as with DNL, the INL of a converter is by definition independent of gain and offset errors. INL calculation [3], [4], [5]:



Offset is the deviation of bottom endpoint from its ideal location [3]. Gain error is the deviation of top endpoint from its ideal location with offset removed [3]. Simulation results are presented in table 2. The results of Monte-Carlo simulation of transfer curve is shown on figure 6. The results of noise analysis is presented in figure 7.




Simulation results

Power consumption

25 μW


<0.2 LSB


< 0.15 LSB

Gain error

0.5 LSB


0.05 LSB


200 nA



Fig. 6. Monte-Carlo results of transfer function


Fig. 7. Noise simulation of transfer function

Layout of the proposed DAC was designed in Cadence Virtuoso Layout XL and verified by using Calibre tool of Mentor Graphics Company. The chip was fabricated by UMC 180 nm CMOS technology available through Europractice foundation. The area of the designed layout is 190 by 100 μm2. Experimental results were obtained by using following instruments: pulse function arbitrary generation by Keysight 81160A, at laboratory conditions by usage Agilent oscilloscope DSO9104H, probe station of Cascade Michrotech. For DNL, INL, gain error and offset calculation Mathlab program package was used. Figure 8 and figure 9 show DNL and INL respectively, the maximum DNL and INL are 0.25 LSB and 0.2 LSB respectively. Offset error is 0.7 LSB, gain error is 3.5 LSB.


Fig. 8. Differential nonlinearity


Fig. 9. Integral nonlinearity


Characteristics of the proposed DAC


UMC 180 nm

Supply voltage

1.8 V


5 bits

Power consumption

25 μW


0.2 LSB




< 0.019 mm2

Gain error

3.5 LSB

Offset error

0.7 LSB



A 5 bit current steering low power area efficient DAC has been designed in UMC 180 nm CMOS technology. Main specifications are presented in table 3. The DAC was designed in binary weighted architecture. To reduce nonlinearity two voltage driven transistors with maximum channel length were used in each current source. The power consumption is 25 μW at 1.8 V power supply. Presented DAC was integrated as a building block into prototype readout channel for CBM experiment being currently under construction at FAIR. This work is done in full accordance with grant No. 14.A12.31.0002. At the same time advanced computer equipment and microelectronic CADs and also control and measuring equipment, deployed in the laboratory under the grant, were used.



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