Experience of designing application readout ASIC in the ASIC Lab of NRNU MEPhI
The Laboratory of ASIC design was created on the basis of NRNU MEPhI (ASIC Lab) under the contract No. 14.A12.31.0002 in the premises NRNU MEPhI total area of 110 m2. The Infrastructure of the ASIC LAB includes a seminar cluster, design lab, test laboratory (clean room).
The seminar cluster of the established laboratory is used to conduct workshops and design courses. Using the means of the seminar cluster, we held two All-Russian Conferences on the Design with the Cadence CAD  .
The design cluster is equipped with everything needed for design - these were acquired two powerful servers (16 cores at 3.2 GHz), and 15 client stations, the design is carried according to the client-server scheme. In the lab servers there have been installed advanced software of computer-aided design (CAD) of the US companies Cadence Design Systems and Mentor Graphics. The laboratory has licensing agreements with several leading companies (TSMC, GlobalFoundries, UMC, AMS, AMIS, Micron) to provide design kits for designing with design rules from 350 to 40 nm. The designed chips are manufactured via the European Europractice organization – NRNU MEPhI is leader by the number of manufacture runs among Russian companies (fig. 1) .
Figure 1 Number of manufacture runs among Russian companies.
The fabricated chips are tested in the laboratory and measuring cluster ASIC LAB. For accurate measurements in NRNU MEPhI these was created a clean zone of the ISO class 7, and purchased the latest Agilent and National Instruments measuring equipment, as well as a Cascade probe station(fig.2) and antistatic furniture. The created cluster ensures accurate testing of analog-digital ASICs.
Figure 2 Measuring equipment and probe stationt
The main directions of the laboratory works are: equipment for large physics experiments, specialized electronics for the aerospace industry, the chips for solving some applied mathematics. The leading scientist of ASIC Lab Samsonov VM has extensive an experience in the development of equipment for the international experiments such as STAR, Fenix, Atlas, CBM.
One of the applications that the laboratory is working at, is the creation of multi-channel electronics for the gas (GEM) detectors of the muon chambers compressed baryonic matter (CBM) at the FAIR accelerators (Darmstadt, Germany) . GEM detectors will be operating at a high gas gain in the range of 1000 to 8000. The MUCH set up has 25,000 64-channel chips to handle totally 1.5x106 channels. Also the GEM muon chambers will have projective segmentation with the smallest pad size being as small as 4.1 x 4.1 mm2 in the inner region and as large as 2.1 x 2.1 cm2 in the outer region of the chamber. This sets up the following ASIC features:
- Dynamic range of 1 - 100 fC;
- Wide Cdet range of 1 - 50 pF;
- S / N maximization at the periphery pads;
- Hit rate up to 1 MHz at the central pads;
- Low (less than 10 mW / channel) power consumption;
- Area efficiency for all building blocks and ADC as the most critical one.
The route design complexity analog-digital chips consist of several steps of chip prototyping. At the first stage the IP blocks of which the chip consists are designed. The next interaction watches the IP units with each other and composes them together, to form a system. If the results of laboratory testing of the system meet the specifications for the chip the design is performed and full-scale chip launched. Otherwise some additional launches of IP blocks and other elements of the system are carried out to ensure the operation of the system.
At the present moment there have been made 4 launches of the chip prototype of the ASIC, reading out the muon chamber signals.
The first prototype ASIC (fig. 3) contains two preamplifier versions . One version includes a traditional structure of a charge-sensitive amplifier (CSA), followed by the shaper. In the other version of the preamplifier, the shaper functions are integrated into the CSA schematic. Due to passive elements, the area occupied on chip by the channel version containing the separate shaper is much larger than the alternative version (1050 × 100 um2 versus 200 × 100 um2). Both versions of processing channels ensure commensurable noise characteristics. In this case, the structure with a separate second order shaper allows us to reach the necessary noise characteristics at a lower power consumption than the version without shaper. At the same time, due to the large area occupied by the passive elements of the standalone filter (the versions differ in areas by a factor of 5), the version with the filter becomes less preferable for use in multichannel systems.
Figure 3 First prototype CBM MUCH
The second prototype (fig. 4) includes 8 analog processing chains, 2 threshold DACs, 8 SAR ADCs and a digital part) .
Each analog channel contains the preamplifier, followed by two shapers (fast and slow) and differential comparator. The preamplifier is based on the folded cascode CSA architecture with additional gain boosting. The preamplifier gain is set to 5 mV / fC and its noise level is estimated by ENC = 1000 el at 50 pF. Since CBM MUCH GEMs will have different granularity, the requirements to the front-end electronics are also different for the central and peripheral parts. Thus, the preamplifier is followed by two chains: a slow channel optimized for S / N ratio in order to use it in the periphery, and a fast channel, adapted to the hit rate of the inner detector part, where the occupancy is the highest. Both channels are realized with CR-RC shapers with different peaking times, 60 ns and 260 ns accordingly.
The structure of the prototype includes a single-ended 40 MS / s 6-bit SAR ADC  with asynchronous architecture and an internal high speed 500MHz clock, generated by dynamic comparator, is used. Moreover, a fully dynamic comparator with near to zero static power consumption. That flip-flop type uses gate capacitance to store the input. Clocking at 500MHz allows to save up to 80% of power, comparing with a conventional D flip-flop, based on NAND gates.
The digital control and readout block plays the role of the backend part of ASIC. Backend collects data from the ADC and organizes their serial output from the chip. For the data exchange the non-standard protocol was implemented. Backend operating frequency is 320 MHz.
The main parameters of the first ASIC prototype are: dynamic range of 100 fC, ENC of 1000 e- at 50 pF, power budget of 10mW per channel. Its structure contains area efficient (0.0255mm2) 1.2mW at 50 Msps 6-bit SAR ADC in each channel.
Subsequent testing showed the prototype performance, however, revealed problems with the system elements in the crystal - error shred generation and ADC digital logic, poor accuracy of threshold DAC, self - excitation in the comparator block.
Figure 4 Second prototype CBM MUCH
The test chip (fig. 5) (CBM TEST) includes the units of ADC-DAC, SLVS transmitter and receiver, the digital unit of information acquisition. The SLVS transmitter consumes 4.9 mW at 1.8 V supply voltage and provides transmission speed up to 320 Mbps and 2 mA output current. The SLVS receiver consumes 500 uW at a 1.8 V supply voltage and a 320 Mbps speed. The optimized DAC circuit is more resistant to the technological spread has improved parameters of integral nonlinearity, full scale error and a reduced power consumption. The basic DAC parameters are: LSB = 200 nA, power consumption of 25 mW, the bit numbers of 5 occupied area- 206 x 100 um. The errors in the ADC circuit have been corrected namely the errors in the performance of comparator and digital logic. The main parameters of the ADC are: bit numbers - 6, LSB- 28 mV, effective number of bits - 5.86, SINAD- 37 dB, SNR- 37 dB SFDR -43,3 dB, power consumption 2 mW, signal frequency - 500 kHz, sampling frequency - 40 MS / s, occupied area - 176 x 90 um2.
The design of the digital data acquisition and output unit – has been completed signals are receiving a frequency of 40 MHz and put out at a frequency of 320 MHz, the unit’s power consumption - 10 mW occupied area - 460 x 360 um.
Figure 5 ASIC with test blocks (CBM TEST)
Using the experience of designing the second prototype of the CBM TEST ASIC, there was developed the third chip (fig. 6)  prototype for the detectors of the CBM MUCH muon chambers.
The structure of the prototype includes: 2 full readout channels, 2 SAR ADCs, Digital control, DACs, Timestamp, Digital peak detector, SLVS Transmitter & Receiver, ELT test blocks. Blocks of readout channels, ADC, DAC, SLVS Transmitter & Receiver were taken from the second prototype ASIC and CBM TEST. Significant changes have been made in digital logic unit (Backend) which includes Digital control units, Digital peak detector, Timestamp. The Backend performs the following functions - provides operations of data exchange and output of results, control operations of ADC and DAC performance, clock generation, time stamp fixation, the formation of the code of the input signal peak value.
Figure 6 Third prototype CBM MUCH
Prototypes of the detectors have been studied with the prototype front-end ASIC (fig. 7, 8). A prototype (fig. 9) read-out system is being developed jointly by PNPI and NRNU MEPhI. The system prototype includes the gas-filled detector based on the GEM and TGEM technologies, gas and high voltage (HV) system and the front-end electronic prototype. To get the stable GEM diode voltages, active dividers are used in the HV system. The front-end prototype consists of the test PCB with the read-out ASIC with the external transient voltage suppressors (TVS). TVS were used to prevent the input ASIC breakdowns due to the GEM detectors sparks. The Test PCB includes the input/output analog and digital interface for data exchange with FPGA processing board. The low-power voltage distribution system on PCB utilizes the FEASTMP DCDC converter. As a multichannel analyzer the CAEN DT5742 digitizer was used. The measurements were carried out with the Ar/CO2 gas mixture and the 55Fe source. 55Fe spectrum were obtained. The measured noise of 1000 electrons at 20pF input capacitance increases up to 2500 electrons at input capacitance of 80 pF.
Figure 7 Prototype of detectors and test board
Figure 8 Measured ASIC with equipment
Figure 9 Manufactured third prototype
Analyzing the results of studding third prototype, there is designed of 32-channel chip, which includes the following options - full-size BackEnd, 8-bit SAR ADC, an improved peak detector, I2C and the Protocol MUCH ASIC – GBTx. The works on designing the chip for reading out the signals from the detectors of the muon chambers are carried out in accordance with the plan described in the TDR.
 IV All-Russian Educational Methodies seminar on the CAD for integrated circuits, 29-31 October, 2013 NRNU MEPHI (http://www.poisknews.ru/theme/edu/8212/)
 V All-Russian scientific methodies seminar on the CAD for integrated circuits intendent for physical experiments 9-10 December 2014 NRNU MEPHI http://cad.mephi.ru/
 EUROPRACTICE ACTIVITY REPORT 2015 (http://www.europractice-ic.com/docs/2015%20europractice_activity%20report.pdf)
 B. Friman et al. eds., The CBM Physics Book, Springer, Heidelberg Germany (2010).
 E. Atkin, E. Malankin and V. Shumikhin, A preamplifier for the muon system of the CBM experiment, Instrum. Exp. Tech. 57 2014pg. 286.
 E. Atkin et al., Development of the read-out ASIC for muon chambers of the CBM experiment, 2015 JINST 10 C04006.
 D. Osipov, A 50MS/s low-power 8-bit dynamic voltage comparator in 0.18mm CMOS process in Proceedings of 29th International Conference on Microelectronics - MIEL 2014, Belgrade Serbia 2014, pg. 439.
 E. Atkin et al., Development and experimental study of the readout ASIC for muon chambers of the CBM experiment, 2016 JINST 11 C01084
 E.V. Atkin, E. Malankin, V. Shumikhin, A. Voronin et all (The CBM Collaboration) Technical Design Report for the CBM Muon Chambers (MuCh) 2014.